In response to Western technology restrictions, Huawei has advanced its artificial intelligence hardware capabilities, improving manufacturing yields for its Ascend 910C chips while introducing the next-generation Ascend 920. Rather than pursuing peak per-chip performance, where it faces external constraints, the firm employs a scale-out strategy embodied by its CloudMatrix 384 system. This architecture aggregates 384 processors to achieve impressive system-level metrics—including roughly 300 PFLOPS and superior aggregate memory bandwidth compared to some rival offerings—even though individual Ascend chips lag behind competitors. This distributed approach is critically enabled by Huawei’s use of all-optical networking technology at scale, notably deploying thousands of Linear Pluggable Optical (LPO) transceivers.
Underpinning this strategy is Huawei’s extensive vertical integration, covering aspects from semiconductor equipment development to its own software stack, granting it significant supply-chain resilience. This allows Huawei to capitalize effectively on the market space vacated by restricted Western firms, increasingly supplying major Chinese technology companies seeking high-performance AI hardware. Nonetheless, substantial challenges persist: Huawei’s systems exhibit considerably lower energy efficiency than alternatives like NVIDIA’s, manufacturing remains limited to less advanced processes due to export controls, and geopolitical scrutiny complicates global adoption. The underlying technical gap in per-chip performance necessitates Huawei’s large-scale, interconnected system design, forging a distinct architectural path shaped by both innovation and constraint.